1. Technical Field
The present invention relates to data processing in general, and in particular to a storage architecture within a data processing system. Still more particularly, the present invention relates to a behavioral memory mechanism for performing fetch prediction within a data processing system.
2. Description of the Related Art
Enabled by technological and algorithmic innovation, computer systems have evolved significantly from their humble origins as mechanical tabulating machines. Major enhancements have greatly increased the utility and economic efficiency as well as the computational scope of computing machinery by several orders of magnitude. While much focus is given to technological evolution, also of great significance is the accompanying innovation in architecture. One of the first key architectural enhancements, which gave birth to the modem computer (i.e., the Von Neumann machine), was the enablement of the computer memory from being utilized for maintaining only data values to being utilized for maintaining instructions also. Prior to such, instructions were fed to a processing unit as a stream from an external source. The ability to maintain instructions in the computer memory enables programs to alter their own flow based upon the data values they processed. In addition, economic efficiency can be realized by utilizing the same computer memory for storing both instructions and data.
As demands for each computing resource being able to serve multiple purposes grew, architectures had also evolved to incorporate multiprogramming (or time-sharing) capabilities. In such domains, aspects of the architecture were enhanced to provide management authority to a supervisory program, hiding certain features of the computer from application programs. Maintained by the supervisory program, virtual memory emerged to provide an economical enablement medium for time-sharing. Virtual memory itself was enabled in part by providing a new enhancement that utilized existing real memory, called a page table; and in part by a portion of the supervisory program. The page table acts as a switchboard through which the supervisory program authorizes and connects the virtual memory accesses of application programs to a real memory in which their data values or instructions are actually stored. In addition, under-utilized portions of the virtual memory can be swapped to a slower and cheaper medium such as disk storage, while retaining only current or frequently used portions of the virtual memory in the real memory.
Many microarchitectural mechanisms for improving performance rely upon retaining a history of past behavior from which they learn to more accurately predict new behaviors. Examples of mechanisms for storing behavioral history information include data caches, instruction caches, branch prediction mechanisms, fetch prediction mechanisms, etc. By nature, such behavioral history information is microarchitecture specific, and hence, not architecturally visible (i.e., not included in the programmer/machine interface specification). Making behavioral history information architecturally visible would result in undesirable complexity and discontinuity for the architecture. Thus, the tracking of such information still falls on the realm of microarchitecture, and the burden of the management thereof also falls on the microarchitecture. The behavioral history information is typically maintained in tables and buffers constructed of expensive, high-speed logic within a processing unit. As a result, the sizes of those tables and buffers are severely constrained.
The present disclosure provides a behavioral memory mechanism for enhancing microarchitectural performances within a data processing system.
In accordance with a preferred embodiment of the present invention, a data processing system includes a processor, a real memory, an address converter, a fetch prediction means, and an address translator. The real memory has multiple real address locations, and each of the real address locations is associated with a corresponding one of many virtual address locations. The virtual address locations are divided into two non-overlapping regions, namely, an architecturally visible virtual memory region and a behavioral virtual memory region. The address converter converts an effective address to an architecturally visible virtual address and a behavioral virtual address. The architecturally visible virtual address is utilized to access the architecturally visible virtual memory region of the virtual memory and the behavioral virtual address is utilized to access the behavioral virtual memory region of the virtual memory. Stored within the behavioral virtual memory region of the virtual memory, the fetch prediction means provides a behavioral virtual address of a next fetch instruction block. The address translator translates the behavioral virtual address of a next fetch instruction block predictor to a real address associated with the real memory.